Nonvolatile semiconductor memory device and method for manufacturing the same

ABSTRACT

A nonvolatile semiconductor memory device having a memory cell portion and peripheral circuit portion is disclosed. The nonvolatile semiconductor memory device has peripheral transistors formed in the peripheral circuit portion of a silicon substrate and cell transistors formed in the memory cell portion of the silicon substrate. The gate length of the cell transistor is shorter than the gate length of the peripheral transistor. Further, the nonvolatile semiconductor memory device has a silicon nitride film selectively formed on the memory cell portion. The silicon nitride film covers the cell transistors.

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application is based upon and claims the benefit of priorityfrom the prior Japanese Patent Application No. 11-118115, filed Apr. 26,1999, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

[0002] This invention relates to a nonvolatile semiconductor memorydevice and a method for manufacturing the same.

[0003] As is well known in the art, a semiconductor memory has celltransistors and peripheral transistors formed on the same substrate. Asone example thereof, an electrically erasable and programmable read onlymemory in which data erasing and programming can be electricallyeffected is well known.

[0004]FIG. 1 shows an EEPROM. That is, FIG. 1 schematically shows theconstruction of cell transistors (including selection gate transistors)and peripheral transistors of a conventional NAND type EEPROM.

[0005] The construction of the cell transistor and peripheral transistorof the NAND type EEPROM is explained below according to themanufacturing process thereof.

[0006]FIGS. 2A to 2D show the manufacturing process of the celltransistors and peripheral transistors of the conventional NAND typeEEPROM.

[0007] First, as shown in FIG. 2A, for example, after a well region andelement isolation region (neither of them is shown in the drawing) areformed in the surface area of a silicon substrate 101, a thermaloxidation film 102 used as a gate insulating film or tunnel oxide filmis formed on the well region.

[0008] Then, in the memory cell region, gate electrodes 103 of stackedgate structure are formed on the thermal oxidation film (tunnel oxidefilm) 102 and, in the peripheral circuit region, gate electrodes 104 ofsingle-layered structure are formed on the thermal oxide film (gateinsulating film) 102.

[0009] The gate electrode 103 in the memory cell region has a well knownstructure in which, for example, a control gate electrode 103 c isstacked on a floating gate 103 a used as a charge storing layer while anONO film (oxide film/nitride film/oxide film) 103 b used as aninter-gate insulating film is disposed therebetween.

[0010] Next, as shown in FIG. 2B, post-oxidation films 105 for restoringthe gate electrodes 103, 104 from the processing damage are formed.

[0011] Then, as shown in FIG. 2C, impurity 106 is implanted to formsource and drain diffusion regions of the respective transistors.

[0012] After this, as shown in FIG. 2D, the implanted impurity 106 isactivated by annealing and driven towards the channel region side toform source and drain diffusion layers 106′.

[0013] Next, after an inter-level insulating film 107 is formed on thestructure, contacts 108 and inter-connection layers 109 connected to theelectrodes 104 and contacts 110 and bit lines 111 connected to thesource/drain diffusion layers 106′ are formed to form the celltransistors and peripheral transistors of the structure shown in FIG. 1.

[0014] However, if the conventional cell transistors and peripheraltransistors are formed as described above, the length of the overlaparea of the source/drain diffusion layer 106′ over the gate electrode103 or 104 varies depending on the condition of the annealing processeffected after the impurity 106 is implanted.

[0015] For example, if the annealing process is not sufficientlyeffected and the source/drain diffusion layer 106′ does not overlap andis offset from the gate electrode 103 or 104, the offset portion acts asa parasitic resistor to prevent a sufficiently large drain current fromflowing in the device.

[0016] On the other hand, if the annealing process is excessivelyeffected and the source/drain diffusion layer 106′ extends deeply intothe channel region, the short channel effect becomes significant and thesource-drain withstand voltage is lowered, thereby degrading the devicecharacteristic.

[0017] Generally, the gate length in the memory cell is shorter thanthat in the peripheral transistor. Therefore, the short channel effectin the memory cell tends to become more noticeable. That is, if theannealing process is sufficiently effected for the peripheraltransistor, there occurs a possibility that punch through may occur inthe cell transistor and selection transistor.

[0018] In the case of NAND type EEPROM, since the source and draindiffusion layers 106′ of the memory cells are satisfactory if they canelectrically connect the cells which are serially arranged, it is notnecessary to overlap the source/drain diffusion layer 106′ over the gateelectrode 103. That is, it can be the that the annealing process afterthe impurity 106 is implanted is effected to the least possible degreefrom the viewpoint of the characteristic of the cell transistor andselection transistor.

[0019] Further, in the case of the post-oxidation amount after the gateprocessing, the post-oxidation for sufficiently compensating for theprocessing damage is necessary, but the post-oxidation increases thebird's beak amount. In a case where the memory cell has a short gate, anincrease in the bird beak amount by the post-oxidation (refer to aportion A in FIG. 1, for example) lowers the coupling ratio, degradesthe programming and erasing characteristics and is not preferable.

[0020] In the case of the peripheral transistor, since the gate isrelatively long, it is permitted to sufficiently effect thepost-oxidation (refer to a portion B in FIG. 1, for example).

[0021] Thus, since the NAND type EEPROM includes transistors havingdifferent gate lengths and the post-oxidation amount and the mostsuitable annealing condition for impurity diffusion are differentdepending on the gate lengths of the transistors, the difference causesa main factor which lowers the process margin.

BRIEF SUMMARY OF THE INVENTION

[0022] A first object of this invention is to provide a nonvolatilesemiconductor memory device in which the annealing condition fordiffusion of impurity and post-oxidation amount can be controlledaccording to the gate lengths of transistors to attain the highperformance of the device and a method for manufacturing the same.

[0023] A second object of this invention is to provide a nonvolatilesemiconductor memory device in which an amount of electrons trapped intothe gate insulating film can be reduced and a method for manufacturingthe same.

[0024] In order to attain the first object, a nonvolatile semiconductormemory device according to one aspect of this invention comprises asemiconductor substrate, a first transistor formed in a peripheralcircuit portion of the semiconductor substrate, a gate electrode of thefirst transistor having a first gate length, a second transistor formedin a memory cell portion of the semiconductor substrate, a gateelectrode of the second transistor having a second gate length shorterthan the first gate length, and a first insulating film formed above atleast the memory cell portion, the first insulating film covering thesecond transistor and having a property which makes it difficult for anoxidizing agent to pass therethrough.

[0025] The above nonvolatile semiconductor memory device has the firstinsulating film selectively formed above the memory cell portion. Thefirst insulating film covers the second transistors and has a propertywhich makes it difficult for oxygen to pass therethrough. Therefore, inthe memory cell portion in which the second transistors are formed,oxidation thereof can be suppressed and in the peripheral circuitportion in which the first transistors are formed, oxidation thereof canbe activated.

[0026] Thus, by making the oxidation amount of the memory cell portiondifferent from the oxidation amount of the peripheral circuit portion,the annealing condition for diffusion of impurity and post-oxidationamount for the first and second transistors can be controlled to anoptimum state even if the gate length of the second transistor issmaller than the gate length of the first transistor. Therefore, thehigh performance of the device can be attained.

[0027] In order to attain the second object, a nonvolatile semiconductormemory device according to another aspect of this invention comprises asemiconductor substrate, a transistor formed in a memory cell portion ofthe semiconductor substrate, and a silicon nitride film whose surface isoxidized, the silicon nitride film covers the transistor.

[0028] The above nonvolatile semiconductor memory device has the siliconnitride film having the surface thereof oxidized. In comparison with asilicon nitride film whose surface is not oxidized, in the siliconnitride film having the surface thereof oxidized, the concentration ofhydrogen contained in the film is reduced. Therefore, if the transistorsformed in the memory cell portion are covered with the silicon nitridefilm, an amount of hydrogen moving towards the transistors can bereduced. As a result, for example, it is possible to reduce the amountof hydrogen entrapped into the gate insulating film of the transistor.

[0029] Since the gate insulating film in which an amount of entrappedhydrogen is small can be obtained, an amount of electrons which aretrapped into the gate insulating film each time the electrons move inthe gate insulating film can be reduced. Therefore, it is possible toreduce the amount of electrons trapped into the gate insulating film.

[0030] Additional objects and advantages of the invention will be setforth in the description which follows, and in part will be obvious fromthe description, or may be learned by practice of the invention. Theobjects and advantages of the invention may be realized and obtained bymeans of the instrumentalities and combinations particularly pointed outhereinafter.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

[0031] The accompanying drawings, which are incorporated in andconstitute a part of the specification, illustrate presently preferredembodiments of the invention, and together with the general descriptiongiven above and the detailed description of the preferred embodimentsgiven below, serve to explain the principles of the invention.

[0032]FIG. 1 is a cross sectional view showing a conventional NAND typeEEPROM;

[0033]FIGS. 2A, 2B, 2C and 2D are cross sectional views showing theconventional NAND type EEPROM in the respective main manufacturingsteps;

[0034]FIG. 3A is a plan view showing a NAND type EEPROM according to afirst embodiment of this invention;

[0035]FIG. 3B is a cross sectional view taken along the 3B-3B line ofFIG. 3A;

[0036]FIG. 4 is a circuit diagram showing an equivalent circuit of theNAND type EEPROM;

[0037]FIGS. 5A, 5B, 5C and 5D are cross sectional views showing the NANDtype EEPROM according to the first embodiment of this invention in therespective main manufacturing steps;

[0038]FIG. 6 is a cross sectional view showing a first modification ofthe NAND type EEPROM according to the first embodiment of thisinvention;

[0039]FIG. 7 is a cross sectional view showing a second modification ofthe NAND type EEPROM according to the first embodiment of thisinvention;

[0040]FIG. 8 is a cross sectional view showing a third modification ofthe NAND type EEPROM according to the first embodiment of thisinvention;

[0041]FIGS. 9A and 9B are cross sectional views each showing one exampleof formation of a contact hole;

[0042]FIGS. 10A and 10B are cross sectional views each showing anotherexample of formation of a contact hole;

[0043]FIG. 11 is a plan view showing a fourth modification of the NANDtype EEPROM according to the first embodiment of this invention;

[0044]FIG. 12 is a cross sectional view showing a fifth modification ofthe NAND type EEPROM according to the first embodiment of thisinvention;

[0045]FIG. 13 is a cross sectional view showing a NAND type EEPROMaccording to a second embodiment of this invention;

[0046]FIGS. 14A, 14B, 14C and 14D are cross sectional views showing theNAND type EEPROM according to the second embodiment of this invention inthe respective main manufacturing steps;

[0047]FIG. 15 is a diagram showing the characteristic of the NAND typeEEPROM according to the second embodiment of this invention incomparison with the characteristic of the conventional NAND type EEPROM;

[0048]FIG. 16A is a circuit diagram showing an equivalent circuit of anAND type EEPROM; and

[0049]FIG. 16B is a circuit diagram showing an equivalent circuit of aNOR type EEPROM.

DETAILED DESCRIPTION OF THE INVENTION

[0050] There will now be described embodiments of this invention withreference to the accompanying drawings. In the present embodiments, forexample, a NAND type EEPROM is used as a nonvolatile semiconductormemory device.

First Embodiment

[0051]FIG. 3A is a plan view showing the schematic construction of aNAND type EEPROM according to a first embodiment of this invention andFIG. 3B is a cross sectional view taken along the 3B-3B line of FIG. 3A.

[0052] As shown in FIGS. 3A, 3B, the NAND type EEPROM has a memory cellregion (cell array) 12 and peripheral circuit region 13 formed on asilicon substrate 11, for example.

[0053] In the memory cell region 12, memory cell transistors, selectiongate transistors and the like are formed. In this embodiment,transistors formed in the memory cell region 12 are generally calledcell transistors.

[0054] Further, in the peripheral circuit region 13, transistorsconstituting a memory core circuit including a row decoder, columndecoder, sense amplifiers and the like and transistors constituting anI/O circuit are formed. In this embodiment, transistors formed in theperipheral circuit region 13 are generally called peripheraltransistors.

[0055] An element isolation region 12 b is formed on the surface of thesilicon substrate 11 in the memory cell region 12. The element isolationregions 12 b separate a plurality of stripe-form element regions 12 aformed in the memory cell region 12 and extending in the columndirection. In the element regions 12 a, for example, the surface of ap-type well region formed on the silicon substrate 11 is exposed.

[0056] In part of the element regions 12 a, n-type source diffusionlayers 21 a are formed, and in another part of the element regions 12 a,n-type drain diffusion layers 21 b are formed. Between the sourcediffusion layer 21 a and the drain diffusion layer 21 b, eighteen celltransistors are formed. The eighteen cell transistors are seriallyconnected.

[0057] The cell transistor among the eighteen cell transistors which isconnected to the source diffusion layer 21 a is a source side selectiongate transistor SGS and the cell transistor connected to the draindiffusion layer 21 b is a drain side selection gate transistor SGD. Theremaining sixteen cell transistors except the above two cell transistorsare memory cell transistors ST. The sixteen memory cell transistors STserially connected to one another constitute one unit cell (NAND cell).

[0058] Each of the memory cell transistors ST includes a gate oxide film31, gate electrode 35 and source and drain diffusion layers 21 formed inthe element region 12 a.

[0059] The gate electrode 35 of the memory cell transistor ST of thisexample has a stacked gate structure. The stacked gate structure isconstructed by a floating gate 32 formed on the gate oxide film 31, aninter-gate insulating film 33 formed on the floating gate 32, and acontrol gate 34 formed on the inter-gate insulating film 33. Forexample, the gate oxide film 31 is formed by oxidizing the surface ofthe substrate 11 which is exposed in the element region 12 a. In a NANDtype EEPROM using a tunnel current at the data programming/erasing, thegate oxide film 31 is also called a tunnel oxide film. The floating gate32 stores charges (generally, electrons) to control the thresholdvoltage of the memory cell transistor ST and is also called a chargestorage layer. The inter-gate insulating film 33 isolates the floatinggate 32 and control gate 34 from each other and is formed of a siliconoxide film/silicon nitride film/silicon oxide film (ONO film), forexample. The control gates 34 on the same row are connected to acorresponding one of word lines WL0 to WL15 for selecting the row of thecell array.

[0060] The drain side selection gate transistor SGD of this example hassubstantially the same structure as the memory cell transistor ST exceptthat one of the source and drain diffusion layers 21 is formed of thedrain diffusion layer 21 b.

[0061] Likewise, the source side selection gate transistor SGS of thisexample has substantially the same structure as the memory celltransistor ST except that one of the source and drain diffusion layers21 is formed of the source diffusion layer 21 a.

[0062] The outer surface of the gate electrode 35 is covered with afirst insulating film 37 formed of a silicon nitride (SiN) film with apost-oxidation film 36 disposed therebetween. That is, the firstinsulating film 37 is selectively formed only on the memory cell region12 so as to cover all of the cell transistors ST, SGS, SGD.

[0063] An inter-level insulating film 38 is formed on the firstinsulating film 37. In the inter-level insulating film 38, contacts 39 band 39 a passing through a thermal oxide film (in this example, which isformed of the same thermal oxide film as the gate oxide film 31) formedon the element regions 12 a and the first insulating film 37 andrespectively reaching the drain diffusion layers 21 b and sourcediffusion layers 21 a are formed.

[0064] On the inter-level insulating film 38, bit lines (BL1, BL2, . . .) 40 connected to the drain diffusion layers 21 b via the contacts 39 bare formed in the column direction. In the inter-level insulating film38, source lines (SL) connected to the source diffusion layers 21 a viathe contacts 39 a are formed in a row direction perpendicular to thecolumn direction. Thus, a memory cell array of the NAND type EEPROMshown in FIG. 4 is constructed.

[0065] As shown in FIG. 3B, each of the peripheral transistors CT formedin the peripheral circuit region 13 includes a gate oxide film 31, gateelectrode 41 and source/drain diffusion layers 42, 43.

[0066] The gate electrode 41 of the peripheral transistor CT of thisexample has a gate length larger than that of the gate electrode 35 ofthe cell transistors ST, SGD, SGS. The structure thereof is not thestacked gate structure but is a general gate structure having asingle-layered gate electrode. The general gate structure is hereinafterreferred to as a single-gate structure for convenience in thisspecification.

[0067] Further, the outer surface of the gate electrode 41 is coveredwith only a post-oxidation film 36.

[0068] An inter-level insulating film 38 is formed on the post-oxidationfilm 36. Contacts 44 each passing through the post-oxidation film 36 andreaching the gate electrode 41 are formed in the inter-level insulatingfilm 38.

[0069] Interconnection layers 45 each connected to a corresponding oneof the gate electrodes 41 via the contact 44 are formed on theinter-level insulating film 38.

[0070] Next, one example of a manufacturing method of the NAND typeEEPROM according to the first embodiment is explained.

[0071]FIGS. 5A, 5B, 5C and 5D are cross sectional views showing the NANDtype EEPROM according to the first embodiment of this invention in therespective main manufacturing steps.

[0072] First, as shown in FIG. 5A, an element isolation region 12 b isformed on the surface of a silicon substrate 11 to isolate elementregions 12 a. Since the cross section of FIG. 5A is taken along theelement region 12 a, the element isolation region 12 b is not shown inFIG. 5A. Then, a portion of the substrate 11 (or well region) exposed inthe element region 12 a is subjected to the thermal oxidation process toform a thermal oxidation film. The thermal oxidation film is used as agate insulating film 31. Next, gate electrodes 35 of stacked gatestructure are formed on the gate oxide film 31 in the memory cell region12 and gate electrodes 41 of single-gate structure are formed on thegate oxide film 31 in the peripheral circuit region 13. The above gateelectrodes are both formed to cross the element regions 12 a, forexample. The gate electrodes 35 of stacked gate structure can be formedby use of a well known method. As one example of the method, a methodfor forming a floating gate 32 on the gate oxide film 31, forming aninter-gate insulating film 33 on the floating gate 32 and forming acontrol gate 34 on the inter-gate insulating film 33 is given. Afterthis, the surfaces of the gate electrodes 35, 41 are subjected to theoxidation process. The oxidation process is effected to compensate forthe processing damage of the gate electrodes 35, 41. As a result,post-oxidation films 36 are formed on the surfaces of the gateelectrodes 35, 41. Then, impurity 21′ is ion-implanted into the elementregions 12 a with the gate electrodes 35, 41 and element isolationregion 12 b used as a mask. The impurity 21′ is ion-implanted to formdiffusion layers 21, 21 a, 21 b, 42, 43 of transistors (ST, SGS, SGD,CT).

[0073] Next, as shown in FIG. 5B, a first insulating film 37 formed of asilicon nitride film is deposited on the structure shown in FIG. 5A. Thefirst insulating film 37 is not limited to the silicon nitride film anda film which makes it difficult for an oxidizing agent (oxidizing seed)to pass therethrough at the later annealing time in an oxidationatmosphere may be used.

[0074] After this, as shown in FIG. 5C, the first insulating film 37formed on the peripheral circuit region 13 is removed. When the aboveremoving process is effected, a photoresist pattern covering the memorycell region 12 or a photoresist pattern having an window correspondingto the peripheral circuit region 13 is formed by use of thephotolithography technology, for example. Then, the first insulatingfilm 37 may be removed by effecting a CDE (Chemical Dry Etching) methodusing the above photoresist pattern as a mask.

[0075] Next, as shown in FIG. 5D, the doped impurity 21′ is activated byannealing in the oxidation atmosphere. As a result, the doped impurity21′ is diffused in the depth direction of the substrate 11 and in thelateral direction towards a portion below each of the gate electrodes35, 41. Thus, diffusion layers 21, 21 a, 21 b, 42, 43 are formed.

[0076] As described above, the structure having the memory cell region12 covered with the first insulating film 37, that is, the structureshown in FIG. 5C is subjected to the annealing process in the oxidationatmosphere. At this time, since the first insulating film 37 is notformed on the surface of the peripheral circuit region 13, a largeramount of oxidizing agent reaches the silicon substrate 11 in theperipheral circuit region 13 than in the memory cell region 12.Therefore, the diffusion speed of the impurity 21′ in the peripheralcircuit region 13 is increased so that the source/drain diffusion layers42, 43 will sufficiently overlap the gate electrode 41.

[0077] Since the memory cell region 12 is covered with the firstinsulating film 37, almost no oxidizing agent reaches the siliconsubstrate 11 in the memory cell region 12 even if the structure issubjected to the annealing process in the oxidation atmosphere.Therefore, the impurity 21′ is not so diffused as in the peripheraltransistor CT, thereby making it possible to suppress the short channeleffect.

[0078] In a case where tungsten silicide (WSi) is used for the controlgate 34, it is considered that abnormal oxidation of WSi will occur dueto the annealing process effected in the oxidation atmosphere. Theabnormal oxidation of WSi tends to occur in a portion where the gatelength of the cell transistor ST is small, for example.

[0079] However, in the first embodiment in which the memory cell region12 is covered with the first insulating film 37, the abnormal oxidationof WSi can be suppressed even if WSi is used for the control gate 34since the oxidizing agent can be suppressed from reaching the gateelectrode 35.

[0080] Further, the bird' beak amount for the gate insulating film 31 inthe memory cell region 12 and the post oxidation amount on the side wallof the gate electrode 35 can be reduced by leaving the first insulatingfilm 37 on the memory cell region 12 in comparison with a case where thefirst insulating film 37 is removed. Reductions in the bird's beakamount and post oxidation amount are particularly effective forsuppressing a lowering in the ratio (coupling ratio) of the capacitancebetween the control gate 34 and the floating gate 32 to the capacitancebetween the floating gate 32 and the substrate 11.

[0081] The post oxidation amount can be changed according toformation/non-formation of the first insulating film 37 for theperipheral transistor CT for which it is desired to sufficiently effectthe post oxidation so as to compensate for the processing damage and forthe cell transistors ST, SGS, SGD for which it is not desired toexcessively effect the post oxidation.

[0082] Next, after an inter-level insulating film 38 is formed on thestructure shown in FIG. 5D, contacts 44 and interconnection layers 45connected to the gate electrodes 41 are formed, bit lines 40 andcontacts 39 b connected to the drain diffusion layers 21 b are formedand source lines and contacts 39 a connected to the source diffusionlayers 21 a are formed. As a result, a NAND type EEPROM of a structureshown in FIGS. 3A, 3B is completed.

[0083] In the first embodiment, the peripheral circuit region 13 can beselectively subjected to the oxidation process.

[0084] That is, the annealing process is effected in the oxidationatmosphere with the memory cell region 12 covered with the firstinsulating film 37. Therefore, even in a case where the gate lengths oftransistors are different, it is possible to simultaneously satisfy theannealing condition for impurity diffusion and the post oxidationamount. As a result, reductions in the process margin due to adifference in the optimum annealing condition for impurity diffusion andthe post oxidation amount depending on the gate lengths of thetransistors can be suppressed and this invention is extremely useful forattaining the high performance of the device.

[0085] (First Modification of First Embodiment)

[0086]FIG. 6 is a cross sectional view showing a first modification ofthe NAND type EEPROM according to the first embodiment of thisinvention.

[0087] As shown in FIG. 6, when the first insulating film 37 is removed,it is not necessary to remove the first insulating film for all of theperipheral transistors CT. That is, the first insulating film 37 may beremoved only for the peripheral transistors CT in which it is desired tocause source/drain layers 42-1, 43-1 to sufficiently overlap a gateelectrode 41-1 or the peripheral transistors CT in which it is desiredto sufficiently effect the post-oxidation process.

[0088] (Second Modification of First Embodiment)

[0089]FIG. 7 is a cross sectional view showing a second modification ofthe NAND type EEPROM according to the first embodiment of thisinvention.

[0090] As shown in FIG. 7, like the structure of the gate electrode 35of the cell transistor (ST, SGD, SGS), a gate electrode 41′ of each ofthe peripheral transistors CT can be formed with a stacked gatestructure. In this case, it is sufficient if the interconnection layer45 is electrically connected to at least the first-layered gateelectrode 32 as is well known in the art.

[0091] Further, in the second modification, an inter-gate insulatingfilm 33 can be formed in the gate electrode 41′ of the peripheraltransistor CT. Therefore, the bird's beak amount for the inter-gateinsulating film 33 can be made different in an area where the firstinsulating film 37 is left behind and in an area where it is removed.

[0092] (Third Modification of First Embodiment)

[0093]FIG. 8 is a cross sectional view showing a third modification ofthe NAND type EEPROM according to the first embodiment of thisinvention.

[0094] As shown in FIG. 8, a gate electrode 35′ of the selection gatetransistor SGD (SGS) can be formed with a structure different from thestructure of the gate electrode 35 of the memory cell transistor ST.

[0095] In this example, the inter-gate insulating film 33 is removedfrom the gate electrode 35′ of the selection gate transistor SGD.

[0096] A gate electrode 41″ of the peripheral transistor CT can also beformed with the same structure as the gate electrode 35′ of theselection gate transistor SGD.

[0097] (Fourth Modification of First Embodiment)

[0098]FIGS. 9A and 9B are cross sectional views showing one example offormation of contact hole.

[0099] As shown in FIG. 9A, in the NAND type EEPROM according to thisinvention, the first insulating film 37 is formed on the elementisolation region 12 b and diffusion layer 21 b. In this case, a materialconstituting the inter-level insulating film 38 and a materialconstituting the first insulating film 37 are made different from eachother. Further, as an etchant used for an RIE (Reactive Ion Etching)process for forming a contact hole 39 b, an etchant which easily etchesthe inter-level insulating film 38 and is difficult to etch the firstinsulating film 37 is used. Thus, the etching process can be temporarilystopped at the first insulating film 37.

[0100] By thus temporarily stopping the etching process at the firstinsulating film 37, the etching process is suppressed from acting on theelement isolation region 12 b even if the formation position of thecontact hole 39 b extends over the element isolation region 12 b becauseof the misalignment of the mask, for example.

[0101] After the first contact hole 39 b is formed in the inter-levelinsulating film 38, as shown in FIG. 9B, an etchant used for the RIE(Reactive Ion Etching) process is changed to an etchant which easilyetches the first insulating film 37 and is difficult to etch the elementisolation region 12 b. Then, the first insulating film 37 is etched toform a second contact hole 39 b′ in the first insulating film 37. As aresult, the contact holes 39 b, 39 b′ reaching the drain diffusion layer21 b, for example, are formed in the inter-level insulating film 38.

[0102] With the above contact forming method, the etching process issuppressed from acting on the element isolation region 12 b even if theformation position of the contact hole 39 b extends over the elementisolation region 12 b. Therefore, it is prevented that the elementisolation region 12 b is etched and a hole exceeding over the pnjunction between the diffusion layer 21 b and the substrate 11 isformed. If the above hole is formed, for example, the bit line BLextends over the diffusion layer 21 b and is brought into contact withthe substrate 11. As a result, a junction leak will increase.

[0103] However, in the EEPROM according to this invention, the etchingprocess can be suppressed from acting on the element isolation region 12b even if the formation position of the contact hole 39 b extends overthe element isolation region 12 b. Therefore, an advantage that anincrease in the junction leak can be suppressed can be attained.

[0104] The contact hole 39 b may have a diameter larger than the widthof the element region as shown in FIGS. 10A and 10B. In this case, thecontact hole 29 b overlaps the element isolation region 12 b.

[0105] Thus, an increase in the junction leak can be suppressed in theEEPROM having the first insulating film 37 in the memory cell region 12.It is therefore preferable to leave the first insulating film 37 on thatpart of the diffusion layer in which a contact hole is to be made and anearby part of the diffusion layer, while any other part of the film 37is removed after the annealing is effected in the oxidation atmosphere.FIG. 11 is a plan view of an EERROM of this type, which is the fourthembodiment of the invention.

[0106] (Fifth Modification of First Embodiment)

[0107]FIG. 12 is a cross sectional view showing a fifth modification ofthe NAND type EEPROM according to the first embodiment of thisinvention.

[0108] In the first embodiment, the first insulating film 37 is formedon the post-oxidation film 36, but this is not limitative. For example,as shown in FIG. 12, a second insulating film 51 such as a silicondioxide film (which is also called a TEOS film) which permits anoxidizing agent to pass therethrough and is formed by using material gasof TEOS (Tetra Epoxy Silane) may be formed between the post-oxidationfilm 36 and the first insulating film 37.

[0109] In this case, for example, since the second insulating film 51functions as a stopper when the first insulating film 37 is removed, theprocess margin can be enlarged.

Second Embodiment

[0110] In a case where a silicon nitride film is used as a firstinsulating film 37, there occurs a possibility that the reliability ofthe tunnel oxide film of a memory cell will be lowered since the siliconnitride film contains a relatively large amount of hydrogen and it hasrelatively large mechanical film stress.

[0111] In this case, hydrogen can be extracted from the silicon nitridefilm and the film quality can be improved by subjecting the structure tothe annealing process after deposition of the silicon nitride film inthe oxidation atmosphere. Therefore, the effect for suppressing alowering in the reliability of the tunnel oxide film of the memory cellcan be sufficiently expected.

[0112]FIG. 13 is a cross sectional view showing a NAND type EEPROMaccording to a second embodiment of this invention. Further, FIGS. 14A,14B, 14C, 14D are cross sectional views showing the NAND type EEPROM ofthe second embodiment of this invention in the respective mainmanufacturing steps.

[0113] The second embodiment will be explained together with themanufacturing method thereof.

[0114] First, as shown in FIG. 14A, a silicon substrate 11 (or wellregion) is subjected to the thermal oxidation process to form a gateoxide film (tunnel oxide film) 31 by the same method as that explainedwith reference to FIG. 5A. Then, gate electrodes 35 of stacked gatestructure are formed on the gate oxide film 31 in a memory cell region12 and gate electrodes 41 of single-gate structure are formed on thegate oxide film 31 in a peripheral circuit region 13. After this, thesurfaces of the gate electrodes 35, 41 are subjected to the oxidationprocess. The oxidation process is effected to compensate for theprocessing damage of the gate electrodes 35, 41, and as the result ofthe oxidation process, post-oxidation films 36 are formed on thesurfaces of the gate electrodes 35, 41. Next, impurity 21′ ision-implanted into the silicon substrate 11 (or well region) with thegate electrodes 35, 41 and the element isolation region 12 b used as amask.

[0115] As shown in FIG. 14B, a silicon nitride film 37 is deposited onthe structure shown in FIG. 14A by the same method as explained withreference to FIG. 5B. It is desired that the silicon nitride film 37have a thickness of 50 nm or less.

[0116] Then, as shown in FIG. 14C, the doped impurity 21′ is activatedby effecting the annealing process in an oxidation atmosphere. In thiscase, the silicon nitride film 37 is subjected to the oxidation processto form a surface oxide film 37′. The surface oxide film 37′ is soformed as to have a thickness of, for example, 1 nm to 10 nm. It isdesired that the surface region of the silicon nitride film 37 beoxidized by strong oxidation, such as pyrogenic oxidation, water-vaporoxygen oxidation, ozone oxidation or oxygen-radical oxidiation. This isbecause strong oxidation can efficiently extract hydrogen from thesilicon nitride film 37.

[0117] The silicon nitride film 37 on which the surface oxide film 37′is formed has a concentration gradient in which the hydrogenconcentration gradually becomes higher from the surface side.

[0118] Thus, an influence by the hydrogen in the silicon nitride film 37on the gate oxide film (tunnel oxide film) 31 is reduced and then theimpurity 21′ is laterally diffused towards portions below the gateelectrodes 35, 41.

[0119] As a result, as shown in FIG. 14D, diffusion layers 21, 21 a, 21b, 42, 43 are formed.

[0120] Next, after an inter-level insulating film 38 is formed on thestructure shown in FIG. 14D, contacts 44 and interconnection layers 45connected to the gate electrodes 41 are formed, contacts 39 b and bitlines 40 connected to the drain diffusion layers 21 b are formed, andcontacts 39 a and source lines connected to the source diffusion layers21 a are formed. Thus, a NAND type EEPROM with the construction shown inFIG. 12 is completed.

[0121] For example, as shown in FIG. 15, the hydrogen concentration ofthe silicon nitride film can be lowered and an electron trap amount dVgin the gate oxide film (tunnel oxide film) 31 can be reduced by forcedlyforming the surface oxide film 37′ on the surface of the silicon nitridefilm 37.

[0122] That is, if the surface of the silicon nitride film 37 issubjected to the oxidation process before deposition of the inter-levelinsulating film 38, the hydrogen concentration of the silicon nitridefilm 37 can be lowered and the hydrogen concentration of the thermaloxide film 31 can be lowered. As a result, the electron trap amount dVgin the gate oxide film (tunnel oxide film) 31 can be reduced and thereliability of the tunnel oxide film can be prevented from beinglowered.

[0123] The hydrogen concentration of the thermal oxide film shown inFIG. 15 is expressed by a relative value when it is set at “1” when thesurface oxide film 37′ is not formed.

[0124] Further, for example, the electron trap amount dVg is adifference between the maximum value and minimum value of the gatevoltage occurring in a period 20 seconds when a negative voltage isapplied to the gate and a D.C. constant current of approx. 0.1 A/cm² iscaused to flow in the tunnel oxide film for approx. 20 seconds. In thiscase, the value of dVg becomes larger as the generation amount ofelectron trap in the tunnel oxide film becomes larger.

[0125] With the above construction, the reliability of the gate oxidefilm (tunnel oxide film) 31 can be suppressed or prevented from beinglowered even if the silicon nitride film 37 is left behind on the memorycell region 12.

[0126] In the second embodiment, the silicon nitride film 37 is leftbehind on the peripheral circuit region 13, and it is possible to leavethe silicon nitride film at least on the memory cell region 12 as in thefirst embodiment. In this case, in addition to the effect that thehydrogen concentration of the silicon nitride film 37 can be lowered, anadvantage that the overlap amount or the like of the diffusion layer canbe made different in the peripheral transistor and in the celltransistor can be attained.

[0127] In the second embodiment, the impurity 21′ is doped into thesubstrate 11 before the silicon nitride film 37 is formed, but this isnot limitative. For example, it is possible to dope the impurity 21′into the substrate 11 after the silicon nitride film 37 is formed.

[0128] The silicon nitride film 37 is not always necessary after theannealing process is effected in the oxidation atmosphere. Therefore, itis possible to remove all of the silicon nitride film 37 after theannealing process.

[0129] Further, this invention is not limited to the NAND type EEPROMand can be applied to an EEPROM other than the NAND type EEPROM, forexample, an AND type EEPROM shown in FIG. 16A, NOR type EEPROM shown inFIG. 16B.

[0130] In the first and second embodiments, the post-oxidation film 36is provided on the upper surface of the control gate electrode 34 ofstacked gate structure or on the upper surface of the gate electrode 41of single-gate structure. Nonetheless, the control gates 34 and 41 mayeach comprise a conductive strip and either a silicon oxide film orsilicon nitride film, which is provided on the conductive strip. In thiscase, the post-oxidation film 36 is provided on only the sides of thecontrol gate electrode 34 or only the sides of the gate electrode 41.

[0131] In addition, this invention can be variously modified withoutdeparting from the technical scope thereof.

[0132] Additional advantages and modifications will readily occur tothose skilled in the art. Therefore, the invention in its broaderaspects is not limited to the specific details and representativeembodiments shown and described herein. Accordingly, variousmodifications may be made without departing from the spirit or scope ofthe general inventive concept as defined by the appended claims andtheir equivalents.

What is claimed is:
 1. A nonvolatile semiconductor memory device comprising: a semiconductor substrate; a first transistor formed in a peripheral circuit portion of the semiconductor substrate, a gate electrode of the first transistor having a first gate length; a second transistor formed in a memory cell portion of the semiconductor substrate, a gate electrode of the second transistor having a second gate length shorter than the first gate length; and a first insulating film formed above at least the memory cell portion, the first insulating film covering the second transistor and having a property which makes it difficult for an oxidizing agent to pass therethrough.
 2. The nonvolatile semiconductor memory device according to claim 1, wherein the gate electrode of the second transistor has a stacked gate structure which includes a floating gate formed on a gate insulating film, an inter-gate insulating film formed on the floating gate and a control gate formed on the inter-gate insulating film.
 3. The nonvolatile semiconductor memory device according to claim 1, further comprising: a second insulating film which is different from the first insulating film and formed between at least the second transistors and the first insulating film.
 4. The nonvolatile semiconductor memory device according to claim 1, wherein the first insulating film is used as an etching stopper when contact holes are formed.
 5. The nonvolatile semiconductor memory device according to claim 1, wherein the surfaces of the gate electrodes of the first and second transistors are oxidized.
 6. A method for manufacturing a nonvolatile semiconductor memory device comprising: forming a first gate electrode, which has a first gate length, on a peripheral circuit portion of a semiconductor substrate and a second gate electrode, which has a second gate length shorter than the first gate length, on a memory cell portion of the semiconductor substrate; introducing impurity into the peripheral circuit portion and memory cell portion with at least the first and second gate electrodes used as a mask; forming a first insulating film above at least the memory cell portion, the first insulating film covering the second transistors and having a property which makes it difficult for an oxidizing agent to pass therethrough; and annealing the semiconductor substrate into which the impurity has been introduced in an oxidation atmosphere to diffuse the impurity into the semi-conductor substrate, whereby a first transistor having the first gate electrode and source and drain diffusion layers containing the diffused impurity is formed in the peripheral circuit portion and a second transistor having the second gate electrode and source and drain diffusion layers containing the diffused impurity is formed in the memory cell portion.
 7. The method for manufacturing the nonvolatile semiconductor memory device according to claim 6, wherein at least the second gate electrode is formed by a method including steps of forming a gate insulating film on the semiconductor substrate, forming a floating gate on the gate insulating film, forming an inter-gate insulating film on the floating gate and forming a control gate on the inter-gate insulating film.
 8. The method for manufacturing the nonvolatile semiconductor memory device according to claim 6, further comprising: forming a second insulating film which is different from the first insulating film and formed between at least the second transistors and the first insulating film.
 9. The method for manufacturing the nonvolatile semiconductor memory device according to claim 6, further comprising: forming an inter-level insulating film above the semiconductor substrate after annealing the semiconductor substrate; forming a first contact hole reaching the first insulating film in the inter-level insulating film; and etching a part of the first insulating film which are exposed to the bottoms of the first contact hole and forming a second contact hole reaching a source/drain diffusion region of the second transistor in the first insulating film.
 10. The method for manufacturing the nonvolatile semiconductor memory device according to claim 6, further comprising; subjecting the surfaces of the first and second gate electrodes to an oxidation process.
 11. A nonvolatile semiconductor memory device comprising: a semiconductor substrate; a transistor formed in a memory cell portion of the semiconductor substrate; and a silicon nitride film whose surface is oxidized, the silicon nitride film covers the transistor.
 12. The nonvolatile semiconductor memory device according to claim 11, wherein the silicon nitride film has a thickness of at most 50 nm.
 13. The nonvolatile semiconductor memory device according to claim 11, wherein the thickness of an oxide film on the surface of the silicon nitride film is not smaller than 1 nm and not larger than 10 nm.
 14. The nonvolatile semiconductor memory device according to claim 11, wherein the concentration of hydrogen in the silicon nitride film is not larger than 3×10²¹ atom/cm³.
 15. A method for manufacturing a nonvolatile semiconductor memory device: forming a transistor in a memory cell portion of a semiconductor substrate; covering the transistor with a silicon nitride film; and subjecting the surface of the silicon nitride film to an oxidation process.
 16. The method for manufacturing the nonvolatile semiconductor memory device according to claim 15, further comprising: forming an inter-level insulating film on the semiconductor substrate after subjecting the surface of the silicon nitride film to an oxidation process.
 17. The method for manufacturing the nonvolatile semiconductor memory device, according to claim 15, wherein the surface of the silicon nitride film is oxidized by a method selected from the group consisting of pyrogenic oxidation and water-vapor oxygen oxidation.
 18. The method for manufacturing the nonvolatile semiconductor memory device, according to claim 16, wherein the surface of the silicon nitride film is oxidized by a method selected from the group consisting of pyrogenic oxidation and water-vapor oxygen oxidation. 